Honored Contributor
Honored ContributorSo, if i put the onchip_memory.hex file created by NiosII IDE in QuartusII project directory, then QuartusII software will use it directly to initial The mem_init<num> generics of ligical RAM, am I right?
I have another question: how to ensure that onchip_memory has been initialed correctly during modelsim post-simulation? The following is my idea: In NiosII IDE, I set code/data... memory to onchip_memory, so I hope to observe the CPU signals to ensure that CPU is excuting my code. In modelsim Pre-simulation, it's easy to implement, because SOPC Builder has bring these signals into modelsim wave window for observing, as the following shows: # Display signals from module cpu add wave -noupdate -divider {cpu} add wave -noupdate -format Logic -radix hexadecimal /test_bench/DUT/the_cpu/i_readdata add wave -noupdate -format Logic -radix hexadecimal /test_bench/DUT/the_cpu/i_readdatavalid add wave -noupdate -format Logic -radix hexadecimal /test_bench/DUT/the_cpu/i_waitrequest add wave -noupdate -format Logic -radix hexadecimal /test_bench/DUT/the_cpu/i_address add wave -noupdate -format Logic -radix hexadecimal /test_bench/DUT/the_cpu/i_read add wave -noupdate -format Logic -radix hexadecimal /test_bench/DUT/the_cpu/A_ci_multi_dataa add wave -noupdate -format Logic -radix hexadecimal /test_bench/DUT/the_cpu/A_ci_multi_datab add wave -noupdate -format Logic -radix hexadecimal /test_bench/DUT/the_cpu/A_ci_multi_ipending add wave -noupdate -format Logic -radix hexadecimal /test_bench/DUT/the_cpu/A_ci_multi_status add wave -noupdate -format Logic -radix hexadecimal /test_bench/DUT/the_cpu/A_ci_multi_estatus add wave -noupdate -format Logic -radix hexadecimal /test_bench/DUT/the_cpu/A_ci_multi_n add wave -noupdate -format Logic -radix hexadecimal /test_bench/DUT/the_cpu/A_ci_multi_a add wave -noupdate -format Logic -radix hexadecimal /test_bench/DUT/the_cpu/A_ci_multi_b add wave -noupdate -format Logic -radix hexadecimal /test_bench/DUT/the_cpu/A_ci_multi_c add wave -noupdate -format Logic -radix hexadecimal /test_bench/DUT/the_cpu/A_ci_multi_readra add wave -noupdate -format Logic -radix hexadecimal /test_bench/DUT/the_cpu/A_ci_multi_readrb add wave -noupdate -format Logic -radix hexadecimal /test_bench/DUT/the_cpu/A_ci_multi_writerc add wave -noupdate -format Logic -radix hexadecimal /test_bench/DUT/the_cpu/A_ci_multi_result add wave -noupdate -format Logic -radix hexadecimal /test_bench/DUT/the_cpu/A_ci_multi_clk_en add wave -noupdate -format Logic -radix hexadecimal /test_bench/DUT/the_cpu/A_ci_multi_start add wave -noupdate -format Logic -radix hexadecimal /test_bench/DUT/the_cpu/A_ci_multi_done add wave -noupdate -format Logic -radix hexadecimal /test_bench/DUT/the_cpu/clk add wave -noupdate -format Logic -radix hexadecimal /test_bench/DUT/the_cpu/reset_n add wave -noupdate -format Logic -radix hexadecimal /test_bench/DUT/the_cpu/d_readdata add wave -noupdate -format Logic -radix hexadecimal /test_bench/DUT/the_cpu/d_waitrequest add wave -noupdate -format Logic -radix hexadecimal /test_bench/DUT/the_cpu/d_irq add wave -noupdate -format Logic -radix hexadecimal /test_bench/DUT/the_cpu/d_address add wave -noupdate -format Logic -radix hexadecimal /test_bench/DUT/the_cpu/d_byteenable add wave -noupdate -format Logic -radix hexadecimal /test_bench/DUT/the_cpu/d_read add wave -noupdate -format Logic -radix hexadecimal /test_bench/DUT/the_cpu/d_write add wave -noupdate -format Logic -radix hexadecimal /test_bench/DUT/the_cpu/d_writedata add wave -noupdate -format Logic -radix hexadecimal /test_bench/DUT/the_cpu/d_readdatavalid add wave -noupdate -format Logic -radix hexadecimal /test_bench/DUT/the_cpu/the_cpu_test_bench/W_pcb add wave -noupdate -format Logic -radix ascii /test_bench/DUT/the_cpu/the_cpu_test_bench/W_vinst add wave -noupdate -format Logic -radix hexadecimal /test_bench/DUT/the_cpu/the_cpu_test_bench/W_valid add wave -noupdate -format Logic -radix hexadecimal /test_bench/DUT/the_cpu/the_cpu_test_bench/W_iw But in modelsim Post-Simulation, I can't find the signals listed above. May be after fitting, their names have been changed(Is there any rule or datasheet can explain how name change before and after QuartusII Fitting operation?) or some of them have been optimized. BTW. how could SOPC Builder bring the signals listed above into modelsim wave window automatically? Could you also guide me how to decide the time resolution during modelsim Post-simulation? In modelsim handbook, it says that: "Choosing the resolution You should choose the coarsest resolution limit possible that does not result in undesired rounding of your delays. The time precision should not be unnecessarily small because it will limit the maximum simulation time limit, and it will degrade performance in some cases." As I know, the unit of *.sdf file created by QuartusII is 'ps', base on the words "You should choose the coarsest resolution limit possible that does not result in undesired rounding of your delays." Does it mean that I should choose 'ps' for modelsim simulator resolution limit? Sorry for so many questions... P.S. : the red color of word represents my questions. :) Wish you a happy Christmas!! Thanks again!
