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AIbra11
New Contributor
New ContributorHow to include user vhdl defined package in ModelSim-Altera RTL Simulation?
I can compile my design in Quartus Prime Lite Edition. I can run the RTL Simulation using ModelSi -Altera well. The problem happens when I included a package vhdl file as follows: 1- I created use...
AIbra11New Contributor
New ContributorThank you Richard, however it didn't help,
I actually solved it by adding :
vcom -93 -work work {C:/intelFPGA_lite/Projects/......./Sources/user_pkg.vhd}
to:
C:/intelFPGA_lite/Projects/......./simulation/modelsim/[project_name]_run_msim_rtl_verilog.do
to include it in the list of compiled files
The problem is I have to do this manually, I hope there was a way to configure it automatically from Quartus.
