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it is meant for copy/paste in a top level vhdl that wants to instantiate it. It is good for those of us lazy enough not to copy/paste from entity interface then just changing "entity" word to "component"
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So is there a simple way to have a file with a component declaration in it that I can include in other files where the component is used?
If I use the component in 5 different files, I don;t really want to have to edit the same info in each file. Or is that complicated in VHDL?
Maybe I'm confusing my terminology because I'm relatively new to VHDL (I used AHDL for decades) but the concept of what I want to achieve seems simple. Just like including a header file containing a typedef in C. How do I do that?
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