How to implement a module for accessing single block of on-chip memory in systemverilog?

You need an arbiter. With multiple masters for a single ram, you need some logic to decide who gets to access the ram in any given cycle.

for example:

always @(posedge clk)
begin
  if (we(0) ) begin
    mem_we <= we[0];
    mem_din <= din[0];
  end
  else begin
    mem_we <= we[1];
    mem_din <= din[1];
  end
end
    

Here, channel 0 has priority over channel 1. With several masters, arbitration schemes can get more complicated - modes like round-robin or lowest port priority are pretty common.