MoZdk
Occasional Contributor
Occasional ContributorHow to ignore simulation only ports when mapping to FPGA pins?
A design has a number of simulation ports that should not be tied to FPGA pins.
A VHDL example is shown in the source below, where the sim_only_* ports are for simulation only, thus should not be ...
Use Virtual Pin assignments in the Assignment Editor. That way the logic for the pins will still be implemented but they won't get connected to physical I/O.
