How to I feed a single input clock pin to 2 PLLs

Sree,

Thank you for answering. One of the first things I tried is to instantiate an ALTCLKCTRL. This had no effect, it was still unable to place my PLL. IIRC, without constraining the input to be a global or a regional clock, the tool said it could not place the PLL in 8 places that it tried. I can get the exact error message if it is helpful.

I have placed the EMIF in banks in 3A, 3B and 3C. The input clock pin is in bank 3B, pins Y6/Y7.

The EMIF pll is placec at IOPLL_3B and I believe it duplicates this in 3A and 3C. My pll (when I constrain the input to be a global clock) gets placed in IOPLL_2L.

Even though my input signal is placed where the EMIF wants it (it chose the pin locations), I get warnings from the Timing Analyzer that it cannot determine the master clock for the EMIF pll. It says candidates are inclk_133 (my signal name for the input clock) and emif_0_ref_clk (the input reference to the EMIF pll) which is fed from inclk_133.

As a quick experiment, I removed the connection to my pll and instead fed its reference from an output from the EMIF pll. So, now inclk_133 feeds the EMIF pll, the EMIF pll outputs a clock of same frequency and that feeds 2nd pll (whose outputs are unrelated and in another clock domain) as well as the rest of the FPGA fabric. I get the same exact warning from the Timing Analyzer that it cannot determine the master clock for the EMIF pll with the same 2 candidates. The result of this tells me that my timing analyzer problems are not a result of connecting the 2 plls to the same input clock but rather a problem with the EMIF IP does not like my input clock. Maybe it wants it to have a particular name...

So how to I tell the Timing Analyzer to use one of those clocks for the master? The sdc file for the EMIF is auto-generated and does not look like I should mess with it even if I could decipher it:-).

Thanks,

Bill