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WKapp's avatar
WKapp
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6 years ago

How to I feed a single input clock pin to 2 PLLs

Hello, I am working on a design using Arria 10 GX. I included a DDR4 EMIF IP that wants a reference clock for its PLL(s). This reference clock is placed on a clock input pin. I also need to genera...
SreekumarR_G_Intel's avatar
SreekumarR_G_Intel
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6 years ago
Hello , As of my understanding it is not the tool issue . Actually tool is trying to help to achieve performance of the PLL within the jitter /Skew specified. You can also notice Startix II and Arria 10 are not same architecture. Few questions : Did you try to use ALTCLKCTRL IP before connect to input of the other PLL reference clock? Can I also know PLL bank that you are trying to use? How do you check there is not input to EMIF PLL when you connect the other PLL to same clock ? is that using signal tap ? Thank you , Regards, Sree