How to heat FPGA at max power consumption?
I am new to Intel FPGA.
Is there any code or tutorial about stress FPGA at max power consumption?
I try to use a lot of register, however compiler seems will simplify my design, so that I can't get a higher power consumption design.
here is an example code from Xilinx I use:
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logic sig100tr =0;
always_ff@(posedge clk500) begin
if (rst) begin
sig100tr <=0;
end else begin
sig100tr <=~sig100tr; // a signal with 100% toggle rate at 500MHz
end
end
local param N3=50000;
(*DONT_TOUCH="TRUE"*)
FDCE#( .INIT( 1'b0 ) // Initial value of register (1'b0 or 1'b1) )
FDCE_1 [N3:1] (
.Q( ), // 1-bit Data output
.C( clk500 ), // 1-bit Clock input
.CE( 1'b1 ), // 1-bit Clock enable input
.CLR( 1'b0 ), // 1-bit Asynchronous clear input
.D( sig100tr ) // 1-bit Data input
);