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Altera_Forum's avatar
Altera_Forum
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13 years ago

How to handle this hold time violated?

I have a design, part of the design is : PLL_6us_3us_300ns pll1(.areset(~ireset),.inclk0(clk),.c0(clk_6us),.c1(clk_3us),.c2(clk_300ns),.locked(lock)); always @(negedge clk) begin i...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

if clk_scan is detected as clock then it means you are triggering some other assignments on its edge. You better avoid that though this is not where the hold time is reported.

If clk_300 rising pulse is always in phase with clk then clk_300 is synchronously related to clk and I wouldn't do edge swap.