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One more observation. You are using pll input as sys-clk. I winder if you got any warnings. Moreover I don't see why you use negedge.
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Yes, I got several Warning but not Critical warnings as following:
Warning (332009): The launch and latch times for the relationship between source clock: pll1|altpll_component|auto_generated|pll1|clk[0] and destination clock: pll1|altpll_component|auto_generated|pll1|clk[1] are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0.
Warning (15064): PLL "PLL_6us_3us_300ns:pll1|altpll:altpll_component|PLL_6us_3us_300ns_altpll2:auto_generated|pll1" output port clk[2] feeds output pin "clk_300ns~output" via non-dedicated routing -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance
Warning (332060): Node: CK_Scan was determined to be a clock but was found without an associated clock assignment.
I don't understand these warnings very well. For negedge I used, the reason is I think:
"clk" is input to PLL and "clk_300ns" is output. Their positive edge is aliged in each 600ns (40*15, 300*2), so if I used posedge, whether will it cause racing and adventure？
Thanks very much.
Honored Contributor
