Forum Discussion
Altera_Forum
Honored Contributor
13 years ago --- Quote Start --- Thanks so much, Kaz. That is clear and I will try this later. The only thing is now CK_Scan is two clk period latency, which you have mentioned. How do you think the hold time violated? Why TimeQuest think the launch clock is "clk_300ns", and latch clock is "clk"? For my understand, both launch and latch clocks are "clk". Thanks. --- Quote End --- Latency is one clock only, not two. Hold violation occur commonly with gated clk or bad phase shift. I don't know about your code but it could be timequest is referring to the clocks that are used for your counters i.e. those in the top enable statement.