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Altera_Forum
Honored Contributor
13 years ago --- Quote Start --- Sorry but I just realised you are using clock enable. However your clock enable is a large combinatorial statement. If you break it up by one clock then it could help your hold time, something like below but you need to adjust the figures due to latency if required: always @(negedge clk) begin if (counterScan>14 && counterScan<31) temp1 <= 1; else temp1 <= 0; end if (counterSystemReset>300 && counterSystemReset<321) temp2 <= 1; else temp2 <= 0; end if; if temp1 || temp2 CK_Scan<=clk_300ns; else CK_Scan<=1'b0; end --- Quote End --- Thanks so much, Kaz. That is clear and I will try this later. The only thing is now CK_Scan is two clk period latency, which you have mentioned. How do you think the hold time violated? Why TimeQuest think the launch clock is "clk_300ns", and latch clock is "clk"? For my understand, both launch and latch clocks are "clk". Thanks.