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Altera_Forum's avatar
Altera_Forum
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13 years ago

How to handle this hold time violated?

I have a design, part of the design is : PLL_6us_3us_300ns pll1(.areset(~ireset),.inclk0(clk),.c0(clk_6us),.c1(clk_3us),.c2(clk_300ns),.locked(lock)); always @(negedge clk) begin i...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Sorry but I just realised you are using clock enable.

However your clock enable is a large combinatorial statement. If you break it up by one clock then it could help your hold time, something like below but you need to adjust the figures due to latency if required:

always @(negedge clk)

begin

if (counterScan>14 && counterScan<31)

temp1 <= 1;

else

temp1 <= 0;

end

if (counterSystemReset>300 && counterSystemReset<321)

temp2 <= 1;

else

temp2 <= 0;

end if;

if temp1 || temp2

CK_Scan<=clk_300ns;

else

CK_Scan<=1'b0;

end