How to handle this hold time violated?

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use ck enable i.e. assign to your signal clk scan on the dge of sys_clk then use if statement for clk enable at the rate you want

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Thanks, Kaz. But I didn't understand what you suggested very well. Could you explain it a little more?

I should mentioned a thing is "CK_Scan", this gating clock signal is for a chip output the FPGA, actually it is a output clock signal. And that chip needs the clock signal oscillates in the specific duration (counterScan>14 && counterScan<31 or counterSystemReset>300 && counterSystemReset<321)

Andbesides the gating clock, do you have any idea about the hold time violated I showed?

That is the thing I care most.

Thanks very much.