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The attached image shows negative hold on sys_clk (as the latch clock). You haven't told us anything about this clock.
The safe practice is to avoid gating any clock
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Hi Kaz, Thanks very much for reply. I posted a command from .sdc file:
create_clock -name sys_clk -period 40.0 [get_ports clk]
sys_clk is the basic clock signal "clk". Yes, I know gating any clock is not a good approach. But in this case, I need control the clock signal "CK_Scan" to work in a specific time of each period. I don't know any other better approach. Do you have any suggestion to avoid gating clock in this case?
Thanks very much again.
Honored Contributor
