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Altera_Forum
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14 years ago

How to get quartus_map to generate a netlist file for bottom-up synthesis

I really don't like using GUIs so I like to run everything on the command line. I am just starting to learn the quartus tools so I need some help in switching from my more familiar Xilinx tool flow. With the Xilinx tools I was able to run the XST synthesis tool on a set of source files and have it output/generate a single netlist representing that code (e.g. my_module_A.edf).

However, when I run quartus_map I don't see any netlist file like this being generated. How do I tell the Quartus synthesis tool to output this file?

My standard development approach is to synthesize submodules A, B, and C all separately, and then pull all of those netlists into a top-level wrapper module called MY_DESIGN_TOP. In other words, I want to instanciate modules A, B, and C in the MY_DESIGN_TOP. But modules A, B, and C would already be synthesized into their own individual netlists. Then I would source those EDIF netlist files (rather than the original HDL source) when running quartus_map on MY_DESIGN_TOP. I know how to do this with the Xilinx tools but need a little help with the Quartus software.

I fear that in order to do this though I need to have "incremental compilation" which is disabled in the web-edition. Someone please say it aint so.... :(

Thanks!

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  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    --- Quote Start ---

    "I use Modelsim and testbenches to get everything working nicely before I synthesize the design."

    Okay, so I knew that suggestion was going to come up at some point. Hehe. I tend not to simulate that much anymore purely due to the fact that software-based simulation can just take wayyyyyyyyyyyyyyy too long to complete (or even get any useful data on large designs). Especially when you have to simulate with 'ps' timescale with a *serial* protocol. You could literally wait weeks to see any relevant data. This is why most of my debugging and verification is done using embedded ILAs.

    --- Quote End ---

    I also use the embedded logic analyzer. However, your initial complaint related to performing small HDL code changes and recompiling. If you test individual components in a testbench (one which gets good coverage of the design), then construct more complex designs based on those components, and either simulate (if they don't take too long) or test with the logic analyzer, then you will reduce the need to re-synthesize the design. At that point, I'm not sure there is any advantage in incremental compilation. Those one line changes should be in your software at that point :)

    Anyways, it sounds like you've got a good understanding of what you can and can't do with the free versions.

    Cheers,

    Dave