Forum Discussion
Hi,
Could you attach your design qar file here? To generate a qar file, go to Project>Archive Project
Thanks,
Nurina
- dcattley4 years ago
New Contributor
Sure.
If you build this simple design you will find a top RTl with a QSYS in it.
Within the QSYS is a simple design of an I2C to Avalon-MM master attached to:
1. A SYSID component directly with ID=1
2. A QSYS Subsystem with a SYSID embedded in it with ID=2
3. A Composed QSYS component with a SYSID embedded in it with ID=3
Looking into the generated SYSID instances (source generated by QSYS) it is very easy to see that:
(1) has a timestamp properly generated: assign readdata = address ? 1646427247 : 1;
(2) has a timestamp properly generated: assign readdata = address ? 1646427247 : 2;
(3) does not have the GENERATION_ID (timestamp) flowing to the instance: assign readdata = address ? 0 : 3;
So basically, this does not work when a component is composed instead of included in a system or subsystem directly (this is taken from altera_avalon_sysid_qsys_hw.tcl).
# +-----------------------------------
# | parameters
# |
add_parameter timestamp INTEGER 0
set_parameter_property timestamp DEFAULT_VALUE 0
set_parameter_property timestamp DISPLAY_NAME "Time stamp"
set_parameter_property timestamp TYPE INTEGER
set_parameter_property timestamp UNITS None
set_parameter_property timestamp AFFECTS_GENERATION true
set_parameter_property timestamp HDL_PARAMETER false
set_parameter_property timestamp SYSTEM_INFO GENERATION_ID
set_parameter_property timestamp ENABLED false
set_parameter_property timestamp VISIBLE false
set_parameter_property timestamp DERIVED true
# |
# +------------------------------------dave