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Honored Contributor
Honored ContributorHow to generate two non overlapping clock signals from single clock?
In a design I'd like to use both edges of an external clock signal (EXT_CLK). No other clock signals are available. Now the question: Is it possible to generate two signals CLK1 == EXT_C...
Altera_ForumHonored Contributor
Honored Contributorif the clock is that slow (<2Mhz) , it might just be easier to use some much faster system clock (like 50Mhz) and sample both the clock and data lines. Wait for a rising edge edge of either clock and just sample the data bus.
