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Honored Contributor
Honored ContributorHow to generate two non overlapping clock signals from single clock?
In a design I'd like to use both edges of an external clock signal (EXT_CLK). No other clock signals are available. Now the question: Is it possible to generate two signals CLK1 == EXT_C...
Altera_ForumHonored Contributor
Honored ContributorDoing logic with the clock is pretty much a no-no in FPGAs. The skew will just kill it.
Why not just derrive a 2x EXT_CLK using a PLL? You can lock the PLL so that it is in sync with EXT_CLK.
