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Altera_Forum
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11 years ago

How to generate random numbers in Verilog TB?

As we all know there is a system function $random in Verilog, which can be used to generate the random numbers. I used it in my simulation and call $random() 5 times, then I found each time I simulat...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Verilog behaves this way so if you find a bug, you can repeat the simulation using the exact same set of values and see if you fix eliminates the bug.

You should call $urandom or $urandom_range(minval,maxval) instead of $random. When you simulate, you can provide a seed using a command switch. In ModelSim/Questa, the switch is -sv_seed random. It will display the random seed used for the simulation so you can repeat it with -sv_seed nnnn.