How to generate post-synthesis .vhd files??

Hi all,

Good day to you..

I am using Quartus II v7.2 web edition and target device is CPLDs. I need to instantiate a particular module (e.g. XOR2 gate) at high fanout nets (found using design assistant report) in post-synthesis .vhd files (which is written using primitives).

To perform the same, i have the following two doubts.

1. How to generate post-synthesis .vhd files?

2. Is it possible to instantiate any combinational block at high fanout nets?? if so, how to perform it?? i.e. how to instantiate a HDL combinational modules in post-synthesis technology mapped .vhd file??

Thank you all.