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Altera_Forum
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16 years ago

How to forbid fitter to use M9K for registers?

Hello, All!

I use cyclone-iii starter board (http://www.altera.com/products/devkits/altera/kit-cyc3-starter.html) with EP3C25 chip.

My project really need 64 M9K blocks, about 600 registers and 2400 logic elements

Quartus II (9.0 web edition) does not fit project to EP3C25 because try use M9K for shift registers.

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Error: Selected device has 66 RAM location(s) of type M9K. However, the current design needs more than 66 to successfully fit

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How to forbid fitter to use M9K for registers?

p.s. Sorry for my bad einglish. This language is not native for me.

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    RAM inference for shift registers can be controlled by global synthesis options and individually for design entities and signals by synthesis attributes.

    The Quartus software handbook gives this example how to specify "logic"-ramstyle (don't use embedded RAM) for a register array, it should work in a similar way for shift registers. 

    type memory_t is array (0 to 63) of std_logic_vector (0 to 7);
signal my_ram : memory_t;
attribute ramstyle : string;
attribute ramstyle of my_ram : signal is "logic";

    Another example disables auto shift register recognition for the whole entity 

    entity my_entity is
-- Declare generics and ports
end my_entity;
architecture rtl of my_entity is
attribute altera_attribute : string;
-- Attribute set on architecture, not entity
attribute altera_attribute of rtl: architecture is "-name AUTO_SHIFT_REGISTER_RECOGNITION OFF";
begin
-- The architecture body
end rtl;

    Of course all synthesis attributes can be set in the assignment editor as well.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    Big Thanks, fvm!

    Your help (second variant) has appeared very useful.