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echen73's avatar
echen73
Icon for New Contributor rankNew Contributor
7 years ago

How to fix timing issue

I use Quartus prime with proper sdc constraint to program FPGA(there are several clock/generated_clock in ny design) . However it still have timing violation in the result. When I add/remove some sig...
KhaiChein_Y_Intel's avatar
KhaiChein_Y_Intel
Icon for Regular Contributor rankRegular Contributor
7 years ago

Hi echen73,

You have to check the timing report and see what are the paths that violated timing.

Thanks.

Timing Analyzer Quick-Start Tutorial: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_tq_tutorial.pdf

Intel® Quartus® Prime Timing Analyzer Cookbook: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/manual/mnl_timequest_cookbook.pdf

Introduction to Timing Analyzer(Pro Edition): https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-qpp-timing-analyzer.pdf

Introduction to Timing Analyzer(Standard Edition): https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug-qps-timing-analyzer.pdf