How to find problem in design after compiliation / fitter failure

Thanks for your reply. I doubt this is the case because the report is being created at the same time with the full flow compilation for the device (Terasic DE1-SoC). This is the device line from the report:

Target Family, Device, Board: Cyclone V, 5CSXFC6D6F31C8ES, de1soc:de1soc_sharedonly

This is the device info from the top.fit.rpt file:

; Family                          ; Cyclone V                                       ;
; Device                          ; 5CSEMA5F31C6                                    ;

For me they look like they are for the same device. Are they not?

edit: Taking a closer look at the device codes it seems that 5CSXFC6D6F31C8ES does not match the DE1-SoC board. How can this be? Looking at the Cyclone V product table this would be a Cyclone V SX SoC instead of a Cyclone V SE SoC. Any ideas?

It makes sense the DSPs are the bottleneck, I will look into it and see if I can somehow reduce the DSP usage further. If you have any further ideas regarding how to make the HTML report more accurate (after the full flow compilation i mean) it would be awesome! Thanks again.