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Altera_Forum
Honored Contributor
Honored ContributorHow to ensure proper simulation in ModelSim
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
ENTITY satUpCount ISPORT(clock, en : IN STD_LOGIC;
flag8 : OUT STD_LOGIC);
END satUpCount;
ARCHITECTURE RTL OF satUpCount IS
SI...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- Yes I know. But why is there discrepancy between simulating VHO and VHDL ? Is there some settings/scripts that will ensure the same behaviour ? --- Quote End --- Your description of setup is not quite right. Your first sim is not modelsim but quartus sim. It does not care about sensitivity list apparently. Your second sim is modelsim and cares about sensitivity list. So flag8 is driven only when clk changes.
