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SPraj4's avatar
SPraj4
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6 years ago

how to "duplicate nodes" and "reduce levels of combinational logic" to remove negative slack in timing analysis Quartus??

I am trying to design ddr3 interface using Qsys in Quartus Prime Lite Edition for cyclone V GT (5CGTFD9E5F35C7) Development board. While running timing analysis, I am facing setup and hold violation...
sstrell's avatar
sstrell
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6 years ago

Those solutions are not typically what you would need to do to solve timing issues in an EMIF IP, only if the timing issues extended into the internal logic of your design. Are you using the hard or soft IP? Go back into the IP Parameter editor and double-check all your settings and timing values. Since you say you are using a dev kit, you should try using the example EMIF design that should be included with the download for the kit. The IP settings in the included design would already be set up correctly for that particular kit.

#iwork4intel

  • SPraj4's avatar
    SPraj4
    Icon for New Contributor rankNew Contributor
    6 years ago

    Thank you .

    I am using hard IP. Is that makes difference in parameter setting ??

    And I have already checked IP parameters but will check again.

  • SPraj4's avatar
    SPraj4
    Icon for New Contributor rankNew Contributor
    6 years ago

    As you suggested I tried to find example design for ddr3 and used the IP parameters in my design . I facing following errors (earlier there was no errors):

    Error: Quartus Prime Analysis & Synthesis was unsuccessful. 3 errors, 9 warnings

    Error: Peak virtual memory: 771 megabytes

    Error: Processing ended: Wed Nov 06 17:23:57 2019

    Error: Elapsed time: 00:02:29

    Error: Total CPU time (on all processors): 00:03:45

    The only thing I have changed is ddr3 IP parameters. Please suggest possible solution for it.

    Below is Qsys system I have created(and same has been attached):