Forum Discussion
Altera_Forum
Honored Contributor
14 years ago --- Quote Start --- Thanks very much, Dave. In your reply, you mentioned "a post-synthesis timing simulation", do you mean GTL timing simulation? --- Quote End --- Post-synthesis simulation = simulating the .vo (or .vho) netlist that Quartus creates. You can simulate it without timing, or use the SDF file (.sdo) to add timing delays. Cheers, Dave