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Altera_Forum's avatar
Altera_Forum
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15 years ago

How to define a signal as a clock

Hi,

I'm interfacing an 8032 to an acek1k FPGA and compilation warns of my wr,ale,and G_clk (crystal input) as undefined clocks. I'm using schematic capture for design entry. How do I define these signals as clocks in Quartus II to get rid of the warnings? I'm not sure if it causing timing issues or not.

TIA,

Vic

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    You can specify these pins as individual clocks in the classical timing analyzer setup. But the "timing issues" question can't answered easily because it depends also on the relation of these clocks in your design.