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Altera_Forum
Honored Contributor
18 years agoprocess (iCLK,iRESET_n)
begin if iRESET_n='0' then az_addr_to_sdr <=std_logic_vector'("10000000000000000000000000"); az_rd_n_to_sdr <= '1'; az_wr_n_to_sdr <= '0'; elsif iCLK'event and iCLK = '1' then if state='1' then az_addr_to_sdr <=std_logic_vector'("10000000000000000000000000")+count; az_rd_n_to_sdr <= '1'; az_wr_n_to_sdr <= '0'; az_cs_to_sdr <='1'; tDATA_to_sdr <=(DATA_for_test&std_logic_vector'("11111111111111111111111111111111111111111111111111111111")); oDATA <= "00001111"; -- when state='1' write data to SDRAM else az_addr_to_sdr <=std_logic_vector'("10000000000000000000000000")+count-std_logic_vector'("01000000000000000000000000"); az_rd_n_to_sdr <= '0'; az_wr_n_to_sdr <= '1'; az_cs_to_sdr <='1'; oDATA <= data_from_dq(7 downto 0); -- when state='0' read data from SDRAM end if; end if; end process; process (iCLK, iRESET_n) begin if iRESET_n='0' then count <= std_logic_vector'("00000000000000000000000000"); elsif iCLK'event and iCLK='1' then count <= count + std_logic_vector'("00000000000000000000000001"); if count >= std_logic_vector'("01000000000000000000000000") then state <= '0'; else state <= '1'; end if; end if; end process; That is the whole program I have used. The problem is that i can't read data from SDRAM. Output data is supposed to be "11111111" but the vale displayed are always "00000000". I don't know if I haven't written.