How to deal with muxed clock in TQ?

Hi, everyone!

In my project, clk1m is generated by a pll with input of clk2m. And Module A's clock is a muxed clock. Module B is a simple crossing clock domain module(set_false_path method between clk1m and clk2m cann't be used in this module).

The TQ reports many setup-timing violation between logic drived by clk1m and clk2m in Module A. But clk1m and clk2m will never exits in the same time in Moudle A...