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NuvKFC's avatar
NuvKFC
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4 years ago

How to deal with integrated clock gating cell on FPGA?

I'm a ASIC/SoC prototyping user. I get an ASIC design which include many clock gating by and gate, or gate, and integrated clock gating cell (latch base). From the following page, I know that cl...
SyafieqS's avatar
SyafieqS
Icon for Super Contributor rankSuper Contributor
4 years ago

We do not receive any response from you to the previous reply that I have provided, thus I will put this case to close pending. Please post a response in the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you with your follow-up questions.


p/s: If any answer from community or Intel support are helpful, please feel free to mark as solution and give Kudos.


  • NuvKFC's avatar
    NuvKFC
    Icon for Contributor rankContributor
    4 years ago

    Hi SyafieqS

    Should I response what?

    • NuvKFC's avatar
      NuvKFC
      Icon for Contributor rankContributor
      4 years ago

      I'm trying to transplant SoC's complex clock network to onto the FPGA.

      But I can't find any methodology to teach people how to do that.

      I need to trial and error.