Forum Discussion

NuvKFC's avatar
NuvKFC
Icon for Contributor rankContributor
3 years ago

How to deal with integrated clock gating cell on FPGA?

I'm a ASIC/SoC prototyping user. I get an ASIC design which include many clock gating by and gate, or gate, and integrated clock gating cell (latch base). From the following page, I know that cl...
SyafieqS's avatar
SyafieqS
Icon for Super Contributor rankSuper Contributor
3 years ago

Hi Kf Cc,


Regarding the remaining clock gate with low fanout, you can refer to other recommendation of clock-gating method.


https://www.intel.com/content/www/us/en/docs/programmable/683082/22-2/recommended-clock-gating-methods.html

For clock divider, you may refer to Basic Clock Divider Using -divide_by


[1] https://www.intel.com/content/www/us/en/docs/programmable/683081/22-2/basic-clock-divider-using-divide-by.html


[2] https://www.intel.com/content/www/us/en/docs/programmable/683243/21-3/clock-divider-example-divide-by.html


  • NuvKFC's avatar
    NuvKFC
    Icon for Contributor rankContributor
    3 years ago

    Hi SyafieqS

    Thank you, SyafieqS, very much. I will study that.