How to deal with integrated clock gating cell on FPGA?

Hi SyafieqS

Thank you, SyafieqS, very, very, much.

For speed, I remove all clock divider and most clock gating cell first, which include "and gate" gating, "or gate" gating, and "ICG".

All clocks are directly connected to the source clock.

Do have any suggestions or suggested steps for migrating those clock gating cells and clock dividers into the FPGA from the ASIC?

I afraid of failing on some complex step, and it may be hard to recover because there is too much clock gating cells.

Then, I need to try again.

For example, some ICG with low fanout don't be changed. It's by my guessing.

Thank you very, very, much.