How to deal with integrated clock gating cell on FPGA?

Sorry that correct the typo.

How about integrated clock gating cell(ICG)?

I only know that latch will use many resources to implement it, and global clocks aren't too much.

I only know that FPGA will use many resources to implement a latch.

Global clocks aren't too much to support all clocks.

And integrated clock gating cell(ICG) may cause some clock skew?

Unfortunately, there are many "and gate" clock gating, "or gate" clock gating, and "integrated clock gating" cell in the ASIC design.

Does someone can please tell me whether have a better way to deal with those clock gating cells?

Thank you very much.