Forum Discussion
I'm guessing the last part, where the node locations increment by 3, e.g. N0, N3, N6, N9... are part of a carry-chain, which are not counted as a single logic level since they are much faster. I'm not sure how they're counted. But with the first part there are definitely distinct hops that should count as more than one. Personally, I've done timing closure on designs for ~20 years and have never found "levels of logic" that useful. There are just too many other things going on, such as carry-chain, fan-out, interconnectedness, etc. that it's not that useful. Plus, in the screen-shot above there is so much more info in the Data Path tab. You have a path with many levels, it crosses three LABs(Y112, Y111, Y109), and looks to be placed and routed really well. If you only had one failing path, maybe getting rid of a lab hop would help close timing, but most likely you have a number of paths, and many similar ones that just barely make timing, whereby squeezing this path down into fewer LABs will probably break another path.
My first question would be why are the two endpoints in ALM registers? Do they have retiming restrictions that prevent Hyper-Retiming? When you run report_timing, click on the -extra_info all and it should give you info about retiming restrictions(plus other fun stuff).