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Altera_Forum
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13 years ago

How to constraint design to meet Recovery Timing

Hi, I have a Cyclone III FPGA design. Quartus II generates a few of Recovery Timing violations. The path info is posted here: Info (332115): Report Timing: Found 1 recovery paths (1 violated...
Altera_Forum's avatar
Altera_Forum
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13 years ago

Analyze in TimeQuest, as it gives more information. Is the source register in the DDR controller, or is it something generated outside of the DDR megafunction and driving in? Is it crossing clock domains? (I think it may be, but not sure). I'm guessing this is a false path, but not quite enough info.