Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

How to constraint design to meet Recovery Timing

Hi, I have a Cyclone III FPGA design. Quartus II generates a few of Recovery Timing violations. The path info is posted here: Info (332115): Report Timing: Found 1 recovery paths (1 violated...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Did You add SDC file generated by DDR memory core? And did You run TCL generated by the same core?