How to constrain output for SRAM in TimeQuest?

There are examples about source synchronous design such as SDRAM time constrain, but I wonder how to constrain output for SRAM in TimeQuest?

eg. no clock needed for SRAM, but you must point a clock in the Set Output/Input Delay setup.

The SRAM data is changed with SRAM address latch in read process, but is it right to set the address as clock?

Thanks very much!