How to constrain my project to deal with these red time issues?

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Can you add a register stage just before the divide function. I understand if some designs do not permit the added clock cycle, but it would most likely improve your timing behavior.

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Thanks for you reply!

I will try it. Currently, my divider's denominator is 16bits and numeritor is 24bits. If i change both to 9bits, the divider will work well. It seems that divider's performence will decrease along with the input bit width increase.