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Altera_Forum
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9 years ago

How to constrain HPS I2C Bus?

Hi My design uses a Cyclone 5 FPGA with an HPS that connects I2C Bus 1 SCL and SDA to external pins that connect to an RTC (Real Time Clock) chip with an I2C Bus interface. The HPS software can...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

This is not really a solution, more of an observation. Given the ultra-slow nature of I2C (100Khz or 400Khz), constraining the timing seems superflous.