How to constrain generated clks derived from other generated clks?

Here comes the 3rd question which is found in a similar design: When a regiser is declared as the target of a generated clock, all the timing paths from this register is analyzed with this generated clock, even though some paths are not driven by this generated clock and should be analyzed as a timing path of the master clock domain.

The example is attached. Run the following command and the problem shows.

report_timing -from [get_keepers {inst1}] -to [get_keepers *counter_reg_bit*]

-setup -npaths 100 -detail path_only -panel_name {Report Timing}

The report says the path is analyzed between gen_clk_level_1 and its master clock base_clk. Actually this path should be analyzed in the base_clk domain only.

I tried to add a specific false path as the following

set_false_path -from [get_clocks gen_clk_level_1] -to [get_clocks base_clk]

-through [get_nets inst1]

but this eliminates the actual path -from [get_clocks base_clk] -to [get_clocks base_clk] too.

I know it is a bad coding style to use "ripple clocks", but as I mentioned in the top post I have to deal with it since it is "legacy".

Can anyone show me how to constrain and analyze this timing path under this situation? Or is this an inability of the TimeQuest?

BTW, I really love this STA tool.

Many thanks in advance!!!