How to constrain a source-synchronous desing?

If data clk is inverted or rotated by PLL to any degree, it is then only a helping hand for timing closure to achieve the requirements.

The requirement is tSU/tH non violation at external device with respect to received data clk.

By entering max delay you inform TQ of tSU and min delay for tH.

TQ does not see but delay figures irrespective what it means to user.

TQ is told about these values with respect to data clk and this is what is required.

TQ knows (or should know) what is clking the data registers at FPGA (io registers or so).

We are talking about pin perspective. Any violation at io register is a different matter (end of fpga chain). if it does occur then PLL or inversion may help.