How to constrain a source-synchronous desing?

Inverted or not makes a big difference. As an aside, I noticed the generated clock assignment on the output port has the -invert option. That is only needed if TimeQuest doesn't know there's an inversion going on inside the FPGA. For example, if you do a 180 degree phase shift with the PLL output driving the clock out, or just add an inverter in the path, it knows it is being inverted. The only time I have used the -invert option is when I drive a clock out through an altddio function, but tie the high register to '0' and the low register to '1', which inverts the clock in a way that TimeQuest/Quartus can't recognize.

-----

kaz, I'm not following your last post. I agree with your analysis of the data window, but if the clock being sent out with the data is inverted or not makes a big difference. If it's not inverted, then there is an 8ns setup relationship. If it is inverted, then it is 4ns. This makes a big difference on how it's analyzed and what Quartus must do to meet timing. You've shown Th--valid--tSu in relation to two edges of the latch clock, but there is no reference point. If it's not inverted, those latch edges are at 0, 8, 16, but if it's inverted then those edges are at 4, 12, etc.