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Altera_Forum
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9 years ago

How to constrain a parallel bus from a PLL clock?

Hi. I have a couple of questions about the my design. Basically I have an FPGA which has a big data table which the values are readed and sent to an external DAC. The reading process and the DAC are ...
Altera_Forum's avatar
Altera_Forum
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9 years ago

Hi Dirk,

Ok. It means calculate the multiplication in parallel to accelerate the procedure. But the ALT_MULT instantiation with zero latency is not a well implementation of a product operation? I mean if ALT_MULT uses a DSP multiplier it is not the best described hardware in terms of performance?