How to constrain a parallel bus from a PLL clock?

Hi Duesterberg,

Thank you for the information. Yes as you said I know the effort in hardware to make these types of operations. My question is how long is the delay to perform a multiplication for instance. Below I instantiate the ALT_MULT core with zero latency option. It seems that takes more 11nS to get the result. This mean I have to add an offset of 12 ns in the PLL output which gives the clock to the DAC ? Or if I use the latency options, I can't figure out how wait until get the result.