How to constrain a DDR input with its clock on a general IO pin?

The Cyclone III/IV source-synchronous timing is confusing. You could enter source-synchronous timing constraints, but the timing will be analyzed with micro parameters and not be very good. If it's 500Mbps, it might not pass. But note that the handbook talks about timing these interfaces using TCCS and SW(sampling window) values. In combination with App Note 479:

http://www.altera.com/literature/an/an479.pdf

If you don't use timing constraints, you can directly use the Sampling Window. This can be found in the handbook, and is 400ps for most speed grades(higher for the slowest parts). So if your layout is:

Incoming ADC clock feeds PLL in source-synchronous mode. This PLL drives the DDR input registers through a global. The sampling window is then 400ps, which is really good. You then need to determine how much to phase-shift the clock, so that it is in the middle of the data eye. I didn't look at the datasheet to verify that.

Finally, note that it is possible to have the incoming clock reference the outgoing clock. You basically put a generated clock on the output clock port, then a generated clock on the input clock port whose -source option is the output. Finally, you need to add set_clock_latency assignments to the incoming clock to specify the max and min external roundtrip delays. That all being said, I would probably treat it as a new clock. At 250MHz, the variation is probably going to be large enough that it can't be successfully related back to the main clock. If you just send the data through a phase-comp FIFO, you can then get it back into the main domain without problem.

(Another option is to have the first PLL not drive any internal logic, and instead have the return clock drive all the logic in your FPGA. That way it's all off the same domain.)