How to constrain a DDR input with its clock on a general IO pin?

Your design does not seem safe from timing view point. The ADC clock of 250MHz should not have been supplied from the fpga and the DCO should have used dedicated clock pin. I have been through a similar situation and I am afraid it might not work. One way around it is not to use that DCO, instead use an internal clock output from fpga PLL that emulates the DCO in phase and frequency including board delays and is locked to ADC clock.