How to connect a verilog testbench to my design in Modelsim

Start Modelsim.

1) vlog my_counter.v

2) vlog my_counter_tb.v

3) vsim -t ps my_counter_tb

4) add wave *

5) run 1 us

Cheers,

Dave

PS. I've attached a couple of SystemVerilog testbenches; use vlog -sv when compiling the .sv files.

Thanks, Dave. That works. Is there a way to have it automatically set up those things each time I run ModelSim from the Quartus II RTL Simulation command? Is there a macro or a dofile I need to set up?

-John

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Is there a way to have it automatically set up those things

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Altera and Modelsim sometimes call them .do files, and Modelsim will run them with the do command, eg., do setup_sim.do. However, they're just tcl files, and source setup_sim.tcl is the same thing.

Here's a Modelsim simulation example here:

http://www.alteraforum.com/forum/showthread.php?t=32386

Look at the sim.tcl file.

Cheers,

Dave

Hi Dave,

I followed your suggestions above exactly using the hex_display files. Vlog did compile both hex_display and hex_display_tb. Then the vsim command triggered this message: "WARNING: No extended dataflow license exists". Then I tried to enter a clock waveform manually which caused the little text box to say view -new wave, followed by (in red) "-new not supported in PE". Stuck again. Please advise.

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I followed your suggestions above exactly using the hex_display files. Vlog did compile both hex_display and hex_display_tb. Then the vsim command triggered this message: "WARNING: No extended dataflow license exists".

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I think I've only ever seen that message in Modelsim-ASE if I double clicked on a design ... perhaps you did? Either way, I think you can ignore that message (did a blank sub-window pop up?)

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Then I tried to enter a clock waveform manually which caused the little text box to say view -new wave, followed by (in red) "-new not supported in PE". Stuck again. Please advise.

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You should just be able to type 'add wave *' to add the top-level signals, or view the signals in the design and drag them to the wave window.

Which version of Modelsim are you trying to use?

Cheers,

Dave

Hi Dave,

I was running Quartus 14.0. I uninstalled that to upgrade to 14.1. Now, within Quartus, I find that hex_display_tb.sv does not compile. The error message is:

Error (10170): Verilog HDL syntax error at hex_display_tb.sv(81) near text ";"; expecting "endmodule"

I am unsure how to fix this.

Forging ahead anyway, I opened Modelsim (10.3C) and, again, followed the directions that you posted above. The first two vlog commands ran fine (so why don't they compile in Quartus?), then when I ran the vsim command the hex_display_tb.sv opened in Notepad++. I then fixed the file associations problem in Win7 so that .v and .sv is now associated with Modelsim. Now when I run the vsim command hex_display_tb.sv opens within a text editor that is part of Modelsim. I don't think this is the same problem that I described above, but I need help on this, too. Thanks.

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why don't they compile in Quartus?

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Because Quartus is for synthesis, and _tb.sv is a testbench containing simulation-only constructs.

You should probably start with some basic tutorials on SystemVerilog under Modelsim and get them to compile first.

Cheers,

Dave