How to cast a large std_logic_vector to an array of smaller ones?

Use a function containing a loop that maps the input std_logic_vector into your census_line type, i.e.,

function to_census_line (slv : in std_logic_vector) returns census_line is
    variable result : census_line;
begin
    for i in 0 to 15 loop
        result(i) <= slv(8*i+7 downto i);
    end loop;
    return result;
end function;

This function needs to go after the census_line type definition.

I just typed this directly into the forum, you'll have to debug any VHDL errors :)

Cheers,

Dave

Hi Dave,

Thanks a lot for your suggestion - with a few modifications it works as expected :)

On the downside however, the resource-requirements for this unit increase considerably, just by changing:

    TYPE census_line IS ARRAY(0 TO 15) OF UNSIGNED(7 downto 0);
    TYPE census_block IS ARRAY(0 TO 15) OF census_line;

to:

    TYPE census_line IS ARRAY(0 TO 15) OF std_logic_vector(7 downto 0);
    TYPE census_block IS ARRAY(0 TO 15) OF std_logic_vector(127 downto 0);

and using the conversion method mentioned, my design increases from ~1.1k ALMs to 2.3k ALMs.

Any ideas what is going wrong here?

Thanks, Reggi

Problem solved :)

Using larger std_logic_vectors somehow reduced optimization freedome for quartus.

When I switched to M10K-blocks for instead of registers, resource-useage went down to 1.1k ALMs which is actually great :)

Thanks!

The function just maps the two different data types, it uses zero resources.

As you have determined, the difference was in what your hardware was doing with those data types :)

Cheers,

Dave