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Altera_Forum's avatar
Altera_Forum
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18 years ago

How to avoid negative slack?

Hi, Currently i'm developing an SOPC also with some self developed components. I'm using QII-6.1 and the CyclonII-Nios-Eval board. Clock frequency is 85MHz. Looked fine so far, but during add...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

Could the problem be that one of your components has a chunk of combinational logic which is causing an excessive delay between two registers. In this case adding a multicycle assignment in the right place could help. This has worked for me before.